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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21342-1E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F04
s
DESCRIPTION
The Fujitsu MB15F04 is a serial input Phase Locked Loop (PLL) frequency synthesizer with two 2.0GHz prescalers. A 64/65 or a 128/129 for both 2.0GHz prescalers can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 11.0mA typ. at a supply voltage of 3.0V. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result of this, MB15F04 is ideally suitable for digital mobile communications. s
FEATURES
* High frequency operation * * * * * RX synthesizer : 2.0 GHz max. TX synthesizer : 2.0 GHz max. Low power supply voltage: VCC = 2.7 to 3.6 V Very Low power supply current : ICC = 11.0 mA typ. (Vcc = 3V) Power saving function : IPSTX = IPSTX = 10 A max. Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 On-chip high performance charge pump circuit and phase comparator, achieving high-speed lock-up and low phase noise Wide operating temperature: Ta = -40 to 85C
* * s
PACKAGE
20-pin, Plastic SSOP
(FPT-20P-M03)
MB15F04
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PIN ASSIGNMENT
(TOP VIEW)
GNDRX1 OSCIN GNDTX finTX VccTX XfinTX BSCTX PSTX DoTX BSTX
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Clock Data LE finRX VccRX XfinRX LD/fout PSRX DoRFX GNDRX2
(FPT-20P-M03)
2
MB15F04
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PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 Pin name GNDRX1 OSCin GNDTX finTX VccTX XfinTX I/O - I - I - I Ground for RX-PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the TX-PLL section. Prescaler input pin for the TX-PLL. The connection with VCO should be AC coupling. Power supply voltage input pin for the TX-PLL section. When power is OFF, latched data of TX-PLL is cancelled. Prescaler complimentary input for the TX-PLL section. This pin should be grounded via a capacitor. Analog switch output (BSTX) control for the TX section. Always pull-down the BSCTX pin when not using BSTX. (Do not leave open.) BSCTX = "H"; outputs the DoTX state. BSCTX = "L" ; goes to high impedance. Power saving mode control for the TX-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSTX = "H" ; Normal mode PSTX= "L" ; Power saving mode Charge pump output for the TX-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Analog switch output for the TX selection. Ground 2 for the RX section. Charge pump output for the RX-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the RX-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSRX = "H" ; Normal mode PSRX = "L" ; Power saving mode Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = "H" ; outputs fout signal LDS bit = "L" ; outputs LD signal Prescaler complimentary input for the RX-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RX-PLL section. When power is OFF, latched data of RX-PLL is cancelled. Prescaler input pin for the RX-PLL. The connection with VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (TX-ref counter, TX-Prog. counter, RX-ref. counter, RX-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. Descriptions
7
BSCTX
I
8
PSTX
I
9 10 11 12
DoTX BSTX GNDRX2 DoRX
O O - O
13
PSRX
I
14
LD/fout
O
15 16 17 18
XfinRX VccRX finRX LE
I - I I
19
Data
I
20
Clock
I
3
MB15F04
s
BLOCK DIAGRAM
VccTX
5
GNDTX
3
8
PSTX
Intermittent mode control
(TX-PLL)
3-bit latch LDS SWTX FCTX
7-bit latch
11-bit latch
fpTX
Binary 11-bit Binary 7-bit swallow counter programmable (TX-PLL) counter(TX-PLL)
(TX-PLL)
Phase comp.
Charge Super pump charger
(TX-PLL)
9 DoTX
Prescaler
finTX 4 XfinTX 6
64/65, 128/129 2-bit latch T1 T2 14-bit latch Binary 14-bit programmable ref. counter(TX-PLL)
frTX
(TX-PLL)
Lock Det.
(TX-PLL)
LDTX
10 BSTX
Analog switch
7 BSCTX
2
OSCin
AND OR
frRX
Selector LD frTX frRX fpTX fpRX
T1
T2
Binary 14-bit programmable ref. counter(RX-PLL)
LDRX
14 LD/fout
2-bit latch
finRX 17
15
14-bit latch
Prescaler 64/65, 128/129 LDS SWRX FCRX Binary 7-bit swallow counter
(RX-PLL) (RX-PLL)
(RX-PLL)
Lock Det.
XfinRF
PSRF 13
Intermittent mode control
(RX-PLL)
Binary 11-bit programmable counter(RX-PLL)
fpRX
(RX-PLL)
Phase comp.
Charge Super pump (RX-PLL) charger
12 DoRX
3-bit latch
7-bit latch
11-bit latch
LE 18
Schmitt circuit
Latch selector
Data 19 Clock 20
Schmitt circuit Schmitt circuit
C N 1
C N 2
23-bit shift register
16 1 11
VCCRX
GNDRX1
GNDRX2
4
MB15F04
s
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Symbol VCC VI VO IO TSTG Rating -0.5 to +4.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -10 to +10 -55 to +125 Unit V V V mA C Remark
Power supply voltage Input voltage Output voltage Output current Storage temperature
WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCC Vi Ta Value Min 2.7 GND -40 Typ 3.0 - - Max 3.6 VCC +85 Unit V V C Note VCCTX = VCCRX
Power supply voltage Input voltage Operating temperature
Handling Precautions * This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F04
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ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 3.6 V, Ta = -40C to +85C)
Parameter Power supply current*1 Power saving current*2 Operating frequency finTX finRX OSCin finTX Input sensitivity finRX OSCin Data, Clock, LE PSTX, PSRX, BSCTX Data, Clock, LE, PSTX, PSRX, BSCTX OSCin LD/fout Output voltage DoIF, DoRF, BSTX DoTX/RX, BSTX LD/fout Output current
Symbol ICCTX ICCRX IPSTX IPSRX finTX*3 finRX*3 fOSC VfinTX VfinRX VOSC VIH VIL VIH VIL IIH*4 IIL
*4
Condition TX RX PSTX ="L" PSTX/RX ="L" TX RX - TX-PLL, 50 load (See TEST CIRCUIT) RX-PLL, 50 load (See TEST CIRCUIT) - Schmitt trigger input Schmitt trigger input - - - - - - VCC = 3.0V, IOH = -1.0 mA VCC = 3.0V, IOL = 1.0 mA VCC = 3.0V, IDOH = -1.0 mA VCC = 3.0V, IDOL = 1.0 mA VCC = 3.0V, VOFF = GND to VCC VCC = 3.0V VCC = 3.0V VCC = 3.0V, VDOH = 2.0V, Ta = +25C VCC = 3.0V, VDOL = 1.0V, Ta = +25C -
Min. - - - - 100 100 3 -10 -10 500 VCCx0.7+0.4 - VCCx0.7 - -1.0 -1.0 0 -100 VCC-0.4 - VCC-0.4 - - - 1.0 -11 8 -
Value Typ. 5.0 6.0 0.1*2 0.1*2 - - - - - - - - - -
Max. - - 10 10 2000 2000 40 +2 +2 VCC - VCCx0.3-0.4 - VCCx0.3 +1.0
Unit mA A
MHz dBm dBm mVp-p V V
Input voltage
A - - - - - - - - - - - - 50 +1.0 +100 0 - 0.4 - V 0.4 1.1 -1.0 - -6 mA 15 - A mA A V
Input current
IIH IIL*4 VOH
VOL
VDOH VDOL IOFF IOH*4 IOL IDOH*4 IDOL RON
High impedance cutoff current
DoIX, DoRX, BSTX
Analog switch on BSTX resistance *1: *2: *3: *4: 6
Conditions ; fin TX/RX = 2000 MHz, fOSC = 12 MHz, VCCTX/RF = 3.0 V, Ta = +25C, in locking state. Conditions ; VCCTX/RX = 3.0 V, fOSC = 12.8 MHz, Ta = +25C AC coupling. The minimum operating frequency is specified with a coupling capacitor 1000 pF connected. The symbol "-" (minus) means direction of current flow.
MB15F04
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FUNCTIONAL DESCRIPTIONS
(A < N)
The divide ratio can be calculated using the following equation: fVCO = {(P x N) + A} x fOSC / R fVCO: P: N: A: fOSC: R:
Output frequency of external voltage controlled ocillator (VCO) Preset divide ratio of dual modulus prescaler (64 or 128) Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0 A 127) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-PLL sections, programmable reference dividers of TX/RX PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
CN1 CN2
Destination of serial data
The programmable reference counter for the TX-PLL. The programmable reference counter for the RX-PLL. The programmable counter and the swallow counter for the TX-PLL The programmable counter and the swallow counter for the RX-PLL
L H L H
L L H H
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 T 1
4 T 2
5 R 1
6 R 2
7 R 3
8 R 4
9 R 5
10 R 6
11 R 7
12 R 8
13 R 9
14 R 10
15 R 11
16 R 12
17 R 13
18 R 14
19 X
20 X
21 X
22 X
23 X
CNT1, 2 : Control bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) T1, 2 : Test purpose bit x : Dummy bit (set to either 0 or 1) NOTE: Data input with MSB first.
[Table. 1] [Table. 2] [Table. 3]
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MB15F04
Programmable Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 L D S
4
5
6 A 1
7 A 2
8 A 3
9 A 4
10 A 5
11 A 6
12 A 7
13 N 1
14 N 2
15 N 3
16 N 4
17 N 5
18 N 6
19 N 7
20 N 8
21 N 9
22 N 10
23 N 11
S F W C TX/ TX/ RX RX
: Control bit : Divide ratio setting bits for the TX section or RX section programmable counter (5 to 2,047) A1 to A7 : Divide ratio setting bits for the TX section or RX section swallow counter (0 to 127) SWTX/RX : Divide ratio setting bit for the prescaler (TX section : SWTX, RX section: SWRX) FCTX/RX : Phase control bit for the phase detector (TX section : FCTX, RX section : FCRX) LDS : LD/fout signal select bit NOTE: Data input with MSB first.
CNT1, 2 N1 to N14
[Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 5 6 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 1 1 1 R 2 0 1 1 R 1 1 0 1
Note: Divide ratio less than 5 is prohibited.
Table.3 Test Purpose Bit Setting
T 1 L H L H T 2 L L H H LD/fout pin state Outputs frTX Outputs frRX Outputs fpTX Outputs fpRX
8
MB15F04
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 5 6 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 1 1 1 N 2 0 1 1 N 1 1 0 1
Note: Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Note: Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = "H" Prescaler divide ratio TX-PLL RX-PLL 64/65 64/65 SW = "L" 128/129 128/129
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MB15F04
Table. 7 Phase Comparator Phase Switching Data Setting
FC = H fr > fp fr = fp fr < fp VCO polarity H Z L (1) FC = L L Z H (2)
VCO Output Frequency (1)
Note: * Z = High-impedance * Depending upon the VCO and LPF polarity, FC bit should be set.
VCO Output Voltage
(2)
Table. 8 LD/fout Output Select Data Setting
LDS H L
LD/fout output signal
fout (frTX/RX, fpTX/RX) signals LD signal
Serial Data Input Timing
1st. Data Control bit Invalid data 2nd. Data
Data
MSB
LSB
Clock
t1 LE t0
t2
t5 t4
t3 On rising edge of the clock, one bit of the data is transferred into the shift register.
t6
Parameter
t1 t2 t3 t4
Min
20 20 30 20
Typ - - - -
Max - - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min
30 100 100
Typ - - -
Max - - -
Unit
ns ns ns
10
MB15F04
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PHASE DETECTOR OUTPUT WAVEFORM
frTX/RX
fpTX/RX
tWU LD (FC bit = High) H DoTX/RX Z
tWL
L
(FC bit = Low) DoTX/RX Z
LD Output Logic Table
TX-PLL section
Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state
RX-PLL section
Locking state / Power saving state Unlocking state Locking state / Power saving state Unlocking state
LD output
H L L L
Note: * Phase error detection range = -2 to +2 * Pulses on DoTX/RX signals are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCin input frequency as follows. tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
11
MB15F04
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POWER SAVING MODE (Intermittent Mode Control Circuit)
Setting a PSTX(RX) pin to Low, TX-PLL (RX-PLL) enters into power saving mode resultant current consumption can be limited to 0.1 A (typ.). Setting PS pin to High, power saving mode is released so that the device works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. Thus keeping the loop locked. PS pin must be set "L" at Power-ON. Allow 1 s after frequency stabilization on power-up for exiting the power saving mode (PS: L to H) Serial data can be entered during the power saving mode. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10A per one PLL section. At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF's time constant. As a result of this, VCO's frequency is kept at the locking frequency.
PSTX L H L H
PSRX L L H H
TX-PLL counters OFF ON OFF ON
RX-PLL counters OFF OFF ON ON
OSC input buffer OFF ON ON ON
12
MB15F04
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ANALOG SWITCH (BSCTX Pin)
The analog switch is set on or off by the BSCTX input. When the switch is on, the output of the charge pump (DoTX) is output from the BSTX pin. (The pin goes to high impedance when the switch is off.) Analog switch ON OFF BSCTX H L
As in the example shown in the figure below, placing the analog switch midway through the LPF (LPF1 + LPF2) allows the LPF time constant to be reduced during PLL channel switching so as to speed up the lock up time.
DoTX CHP LPF1 LPF2 VCO
Analog swtch
BSTX
BSCTX
13
MB15F04
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TYPICAL CHARACTERISTICS
Input sensivity of FIN (RX) vs. Input frequency
10 5 0 Vfin RX (dBm) -5 -10 -15 -20 -25 -30 -35 -40 0 1000 2000 fin (MHz) 3000 4000 V CC=2.7 V V CC=3.0 V V CC=3.6 V SPEC Ta = +25C
Input sensivity of FIN (TX) vs. Input frequency
10 5 0 -5 Vfin TX (dBm) -10 -15 -20 -25 -30 -35 -40 0 1000 2000 fin (MHz) 3000 V CC=2.7 V V CC=3.0 V V CC=3.6 V 4000 SPEC Ta = +25C
Input sensivity of OSC vs. Input frequency
10 0 -10 VOSC (dBm0) -20 -30 -40 -50 -60 0 10 50 fOSC (MHz) 100 V CC=2.7 V V CC=3.0 V V CC=3.6 V SPEC Ta = +25C
(Continued)
14
MB15F04
RX Do output current
IDOH - VDOH
Conditions: Ta = +25C
5.000
V CC = 3 V Ta = +25C
V DOH (V) .0000 .0000 I DOH (mA)
-25.00
IDOL - VDOL 5.000 V CC = 3 V Ta = +25C
V DOL (V) .0000 .0000 I DOL (mA)
25.00
(Continued)
15
MB15F04
TX Do output current
IDOH - VDOH
Conditions: Ta = +25C
5.000
V CC = 3 V Ta = +25C
V DOH (V) .0000 .0000 I DOH (mA) IDOL - VDOL
-25.00
5.000
V CC = 3 V Ta = +25C
V DOL (V) .0000 .0000 I DOL (mA)
25.00
(Continued)
16
MB15F04
Input impedance
fin 1; 9.7188 -67.062 500 MHz 8.2324 -17.395 1 GHz 11.075 6.2979 1.5 GHz 12.635 23.558 2 GHz
4
2;
finRX Pin
3
3;
4;
2
1
START 100.000 000 MHz STOP 1 500.000 000 MHz
fin 1; 19.266 -132.09 500 MHz 9.6855 -49.215 1 GHz 11.299 -13.364 1.5 GHz 12.398 10.659 2 GHz
2;
finTX Pin
4
3;
4;
3
1 2
START 100.000 000 MHz STOP 1 500.000 000 MHz
(Continued)
17
MB15F04
(Continued)
Input impedance
OSC IN 1; 28.862 k -33.732 k 1 MHz 77 -4.5602 k 12.8 MHz 114.63 -2.5294 k 23 MHz 112.13 -1.9848 k 30 MHz
2;
OSCin Pin
3; 2 3 4;
4
START .500 000 MHz
STOP 100.000 000 MHz
18
MB15F04
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TEST CIRCUIT (Prescaler Input/Programmable Reference Divider Input Sensitivity Test)
1000pF
VccTX S.G 1000p 0.1F 50
S.G
1000pF
GND 10 9 8 7 6 5 4 3 2 1
50
MB15F04
11 S.G 1000pF 50
12
13
14
15
16
17
18
19
20
VccRX Oscilloscope 1000 pF 0.1F
Controller (sets the divide ratios)
19
MB15F04
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APPLICATION EXAMPLE
Output
VCO
Low pass filter
from controller 1000 pF
3V 0.1F 1000 pF
Lock Det.
20
19
18
17
16
15
14
13
12
11
MB15F04
1
2
3
4
5
6
7
8
9
10
1000 pF 3V
TCXO 1000 pF
0.1F
1000 pF
Output
VCO
Low pass filter
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). BSCTX : Always pull-down the BSCTX pin when not using the analog switch output (BSTX). (Do not leave the pin open.)
20
MB15F04
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ORDERING INFORMATION
Part number MB15F04 PFV Package 20pin, Plastic SSOP (FPT-20P-M03) Remarks
21
MB15F04
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PACKAGE DIMENSION
20 pins, Plastic SSOP (FPT-20P-M03) * : These dimensions do not include resin protrusion.
* 6.500.10(.256.004)
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10 6.400.20
(.173.004) (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
5.85(.230)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F20012S-2C-4
Dimensions in mm (inches)
22
MB15F04
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9703 (c) FUJITSU LIMITED Printed in Japan
23

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